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A Bibliography on Capacity Modeling for Semiconductor Manufacturing
Section 38: Yield, Inspection and Quality
 | M. Abe (Texas Instruments), "Wafer Map Merging and Shipping System in
Multi Factory Flow," Proceedings of the 2004 International Symposium on
Semiconductor Manufacturing (ISSM 2004), Tokyo, Japan, 2004. |
| R. Akella, S. M. Datar and P. Nandakumar, "Models for Measuring and
Accounting for Cost of Conformance Quality," Report No. XSD-25,
Carnegie Mellon University, 1989. |
| R. Akella, S. Rajagopaian, and M. R. Singh, "Part Dispatch in Random
Yield Multi-Stage Flexible Test Systems for Printed Circuit Boards,"
Operations Research, Vol. 40, No. 4, 776-789, 1992. |
| F. Archetti, A. Gaivoronski, and F. Stella, "Stochastic Optimization
on Bayesian Nets," European Journal of Production Research, Vol. 101,
No. 2, 360-373, 1997. |
| F. Auram and L. M. Wein, "A Product Design Problem in Semiconductor
Manufacturing," Operations Research, Vol. 40, No. 5, 986-998, 1992. |
| F. Bergeret and C. Le Gall, "Yield Improvement using Statistical
Analysis of Process Dates," IEEE Transactions on Semiconductor
Manufacturing, Vol. 16, No. 3, 535-542, 2003. |
| G. R. Bitran and S. M. Gilbert, "Co-Production Processes with Random
Yields in the Semiconductor Industry," Operations Research, Vol. 42,
No. 3, 476-491, 1994. |
| R. E. Bohn, "Noise and Learning in Semiconductor Manufacturing,"
Management Science, Vol. 41, No. 1, 31-42, 1995. |
| C. G. Cassandras and Y. Han, "Optimal Inspection Policies for a
Manufacturing Station," European Journal of Operational Research, Vol.
63, 35-53, 1992. |
| Wen-Chi Chang, M. Yu, R. Wu, C. Chen, J. Chen, C. Y. Hsieh, and C. K. Wang, "Yield Improvement through Cycle Time and Process Fluctuation Analyses," 2001 IEEE International Symposium on Semiconductor Manufacturing (ISSM '01), 267-270, 2001. The authors are from Taiwan Semicond. Manuf. Co., Hsin-Chu. |
| C. F. Chien, K. H. Chang, and C. P. Chen, "Design of a Sampling
Strategy for Measuring and Compensating for Overlay Errors in Semiconductor
Manufacturing," International Journal of Production Research, Vol. 41,
No. 11, 2547-2561, 2003. |
| C-F Chien, S-C Hsu, S. Peng, C-H Wu, "A Cost-Based Heuristic for
Statistically Determining Sampling Frequency in a Wafer Fab," 2000
Semiconductor Manufacturing Technology Workshop, 217-229, 2000. |
| J. W. Clemons, "Statistical Manufacturing Control: An Integrated
Statistical Quality Control System," Proceedings of the 3rd Annual
Conference of the Industrial Computing Society, Chicago, IL, 399-404, 1993. |
| J. A. Cunningham, "The Use and Evaluation of Yield Models in
Integrated Circuit Manufacturing," IEEE Transactions on Semiconductor
Manufacturing, Vol. 3, No. 2, 60-71, 1990. |
| S. P. Cunningham and J. G. Shanthikumar, "Empirical Results on the
Relationship Between Die Yield and Cycle Time in Semiconductor Wafer
Fabrication," IEEE Transactions on Semiconductor Manufacturing, Vol. 9,
No. 2, 73-277, 1996. |
| D. L. Dance and R. Jarvis, "Using Yield Models to Accelerate Learning
Curve Progress," IEEE Transactions on Semiconductor Manufacturing, Vol.
5, No. 1, 41-45, 1992. |
| S.-K. Fan, "Quality Improvement of Chemical-Mechanical Wafer
Planarization Process in Semiconductor Manufacturing using A Combined
Generalized Linear Modelling-Non-Linear Programming Approach,"
International Journal of Production Research, Vol. 38, No. 13, 3011-3029,
2000. |
| L. F. Fuller, K. D. Hirschman, and P. C. Waldrop, "Total Quality
Manufacturing At The RIT Integrated Circuit Factory," Proceedings of
the 11th Biennial University/Government/Industry Microelectronics Symposium,
Austin, TX, 52-56, 1995. |
| G. Gallego, D. D. Yao, and I. Moon, "Optimal Control of A
Manufacturing Process that Involves Trial Runs," Management Science,
Vol. 39, No. 12, 1499-1505, 1993. |
| B. Grosman, S. Lachman-Shalem, R. Swissa, and D. R. Lewin, "Yield Enhancement in Photolithography through Model-Based Process Control: Average Mode Control," IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 1, 86-93, 2005. Authors are from PSE Res. Group, Technion Univ., Haifa, Israel. |
| H. Gurnani, "Optimal Lot-Sizing Policy With Incentives for Yield Improvement," IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 2, 304-308, 2005. |
| H. Gurnani, Z. Drezner, and R. Akella, "Capacity Planning Under
Different Inspection Strategies," European Journal of Operational
Research, Vol. 89, No. 2, 302-312, 1996. |
| H. Gurnani and R. Akella, "Issues in Capacity Planning Under
Different Repair Strategies," Proceedings of the 1990 Japan-USA
Symposium on Flexible Automation, 1113-1118, 1990. |
| N. Hatch and D. Mowery, "Process Innovation and Learning by Doing in
Semiconductor Manufacturing," Management Science, Vol. 44, No. 11,
I461-I477, 1998 |
| A. Hsu and Y. Bassok, "Random Yield And Random Demand In A Production
System With Downward Substitution," Operations Research, Vol. 47, No.
2, 277-290, 1999. |
| Jer-Wei Hsu, Hsi-Lo Lo, Cheng-Chung Pan, Yi-Ming Chen, and Teng-Ko Hsieh, "Test Wafer Control System in 300 mm FAB," Proceedings of the 2004 Semiconductor Manufacturing Technology Conference, 33-36, 2004. The authors are from Powerchip Semicond. Corp., Hsinchu, Taiwan. |
| C. D. Ittner, "Exploratory Evidence on the Behavior of Quality
Costs," Operations Research, Vol. 44, No. 1, 114-130. |
| W. Jang, E. H. Wang, and R. Akella, "Economic In-Line Inspection
Sampling Strategy with Learning Effects," International Journal of
Production Research, Vol. 38, No. 18, 4811-4821, 2000. |
| P. Jula, C. J. Spanos, and R. C. Leachman, "Comparing the Economic
Impact of Alternative Metrology Methods in Semiconductor
Manufacturing," IEEE Transactions on Semiconductor Manufacturing,
Volume 15, Number 4, 454-463, 2002. |
| H. L. Lee and C. A. Yano, "Production Control in Multistage Systems
with Variable Yield Losses," Operations Research, Vol. 36, No. 2,
269-278, 1988. |
| M. D. Longtin, L. W. Wein, and R. E. Welsch, "Sequential Screening in
Semiconductor Manufacturing, I: Exploiting Spatial Dependence,"
Operations Research, Vol. 44, No. 1, 173-195, 1996. |
| I. Moon, "A Send-Ahead Policy for A Semiconductor Wafer Fabrication
Process," Journal of Korean OR Society, Vol. 18, No. 1, 119-126, 1993. |
| K. Mori, N. Nguyen, and S. J. Hsieh, "Prioritizing Efforts to Improve
Yield," International Journal of Industrial Engineering, Vol. 7, No. 4,
275-280, 2001. |
| P. K. Nag, "Yield Forecasting," Ph.D. Dissertation, Department
of Electrical and Computer Engineering, Carnegie Mellon University, 1996. |
| P. Nag, W. Maly, and H. J. Jacobs, "Simulation of Yield/Cost Learning
Curves with Y4," IEEE Transactions of Semiconductor Manufacturing, Vol.
10, No. 2, 256-266, 1997. |
| Y. Narahari and L. M. Khan, "Modeling Re-Entrant Manufacturing
Systems With Inspections," Journal of Manufacturing Systems, Vol. 15,
No. 6, 367-378, 1996. |
| J. Ou and L. M. Wein, "Sequential Screening in Semiconductor
Manufacturing, II: Exploiting Lot-to-Lot Variability," Operations
Research, Vol. 44, No. 1, 196-205, 1996. |
| K. Park, and Y. S. Kim, "Input Quantity Control in A Multi-Stage
Production System with Yield Randomness, Rework and Demand
Uncertainty," Journal of the Korean OR Society, Vol. 18, No. 3,
151-157, 1993. |
| C. K. Shin and S. C. Park, "A Machine Learning Approach To Yield
Management In Semiconductor Manufacturing," International Journal of
Production Research, Vol. 38, No. 17, 4261-4271, 2000. |
| S. Simmons, "Modeling Yield Throughout the DRAM Product Life
Cycle," Proceedings of the 1999 International Symposium on
Semiconductor Manufacturing (ISSM '99), 1999. |
| M. R. Singh, C. T. Abraham and R. Akella, "A Wafer Design Problem in
Semiconductor Manufacturing for Reliable Customer Service," IEEE
Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 13,
No. 1, 103-108, 1990. |
| K. R. Skinner, D. C. Montgomery, G. C. Runger, J. W. Fowler, D. R.
McCarville, T. R. Rhoads, and J. D. Stanley, "Multivariate Statistical
Methods for Modeling and Analysis of Wafer Probe Test Data," IEEE
Transactions on Semiconductor Manufacturing, Volume 15, Number 4, 523-530,
2002. |
| K. Srinivasan, R. Sandell, and S. Brown, "Correlation Between Yield
And Waiting Time: A Quantitative Study," Proceedings of the Seventeenth
IEEE/CPMT International Electronics Manufacturing Technology Symposium:
Manufacturing Technologies - Present and Future, Austin, TX, 65-69, 1995. |
| C. S. Tang, "Composing Batches with Yield Uncertainty,"
Operations and Technology Management Working Paper No. 7-90, The John E.
Anderson Graduate School of Management at UCLA, 1990. |
| C. S. Tang, "Designing an Optimal Production System with
Inspection," European Journal of Operational Research, Vol. 52, No. 1,
45-54, 1991. |
| C. Weber, "Yield Learning and the Sources of Profitability in Semiconductor Manufacturing And Process Development," IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 4, 590-596, 2004. Author is from Dept. of Eng. & Technol. Manage., Portland State Univ., OR, USA. |
| C. Weber, C. N. Berglund, and P. Gabella, "Yield Learning and the Economics of Photomasks," IEEE 2004 Advanced Semiconductor Manufacturing Conference (ASMC '04), 279-284, 2004. Authors are from ETM, Portland State Univ., OR, USA. |
| A. S. Wein, "Random Yield, Rework and Scrap in a Multistage Batch
Manufacturing Environment," Operations Research, Vol. 40, No. 3,
551-563, 1992. |
| L. M. Wein, "On the Relationship Between Yield and Cycle Time in
Semiconductor Wafer Fabrication," IEEE Transactions on Semiconductor
Manufacturing, Vol. 5, No. 2, 156-158, 1992. |
| M. C. Wu, C. W. Chiou, and H. M. Hsu, "Scrapping Small Lots in a
Low-Yield and High-Price Scenario," IEEE Transactions on Semiconductor
Manufacturing, Vol. 17, No. 1, 55-67, 2004. |
| Muh-Cherng Wu, Chie-Wun Chiou, and Hsi-Mei Hsu, "Scrap Rules for Small Lots in Wafer Fabrication," Proceedings of the 2002 Semiconductor Manufacturing Technology Conference, 187-190, 2002. The authors are from Dept. of Ind. Eng. & Manage., Nat. Chiao Tung Univ., Hsic-Chu, Taiwan. |
| Taho Yang, Mu-Chen Chen, Chao-Ton Su, "Quality Management Practice in Semiconductor Manufacturing Industries - Empirical Studies in Taiwan," Integrated Manufacturing Systems, Vol. 14, No. 2, 153-159, 2003. |
| D. D. Yao and S. Zheng, "Sequential Inspection Under Capacity
Constraints," Operations Research, Vol. 47, No. 3, 410-421, 1999. |
| M. Yu, W.-C. Chang, C. Chen, Y.L. Hsieh Chen, C. Y. Hsieh, and C.-K. Wang,
"Development of Waiting Time Control System for Yield enhancement and
WIP Management," Proceedings of the 2002 International Symposium on
Semiconductor Manufacturing, Tokyo, Japan, 2002. |
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