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A Bibliography on Capacity Modeling for Semiconductor Manufacturing
Section 33: Scheduling
 | M. Adams and B. Smoak, "Managing Manufacturing Improvement Using
Computer Integrated Manufacturing Methods," Proceedings of the
IEEE/SEMI International Semiconductor Manufacturing Science Symposium -
ISMSS '90, 9-13, 1990. |
| R. Akella, Y. Choong, and S. B. Gershwin, "Performance of
Hierarchical Production Scheduling Policy", IEEE Transactions of
Components, Hybrids, Manufacturing Technology, Vol. CHMT-7, No. 3, 225-238,
1984. |
| R. Akella, O. Maimon, and S. B. Gershwin, "Value Function
Approximation Via Linear Programming for FMS Scheduling," International
Journal of Production Research, Vol. 28, No. 8, 1459-1470, 1990. |
| A. Arisha and P. Young, "Intelligent Simulation-based Lot Scheduling
of Photolithography Toolsets in a Wafer Fabrication Facility,"
Proceedings of the 2004 Winter Simulation Conference, Washington, DC, Dec.
5-8, 2004. |
| S. Barman, "Simple Priority Rule Combinations: An Approach To Improve
Both Flow Time And Tardiness," International Journal of Production
Research, Vol. 35, No. 10, 2857-2870, 1997. |
| J. J. Bartholdi, III, C. B. Lofgren, and G. G. Sigismondi,
"Scheduling Technology for Semiconductor Fabrication, Technical Report
No. NSF/ISI-88094, National Science Foundation, 1988. |
| P. Baudet, C. Azzaro-Pantel, S. Domenech, and L. Pibouleau,
"Discrete-Event Simulation Approach For Scheduling Batch
Processes," Chemical Engineering, Vol. 19, No. Suppl, S633-S638, 1995. |
| G.R. Bitran and D. Tirupati, "Development and Implementation of a
Scheduling System for a Wafer Fabrication Facility," Operations
Research, Vol. 36, No. 3, 377-395, 1988. |
| G.R. Bitran and D. Tirupati, "Planning and Scheduling for Epitaxial
Wafer Production Facilities," Operations Research, Vol. 36, No. 1,
34-49, 1988. |
| H. Chen and D. D. Yao, "Dynamic Scheduling of a Multi-Class Fluid
Network," Operations Research, Vol. 41, No. 6, 1104-1115, 1993. |
| C. Y. Chiu, W. L. Chou, S. M. Horng, and R. J. Kuo, "A wafer
fabrication dispatching method for minimizing inventory variability using
fuzzy inference," International Journal of Industrial Engineering -
Theory, Applications, and Practice, Vol. 10, No. 4, 621-627, 2003. |
| D. Connors, G. Feigin, and D. Yao, "Scheduling Semiconductor Lines
Using A Fluid Network Model," IEEE Transactions on Robotics and
Automation, Vol. 10, No. 2, 88- 98, 1994. |
| M. Cristofari, M. Tronci, F. Caron, E. McDuffie, "Interaction of
Control Policies In A Flexible Manufacturing system," Proceedings of
the 8th European Simulation Symposium (ESS '96), Genoa, Italy, 298-302,
1996. |
| R. M. Dabbas and J. W. Fowler, "A New Scheduling Approach Using
Combined Dispatching Criteria in Wafer Fabs," IEEE Transactions on
Semiconductor Manufacturing, Vol. 16, No. 3, 501-510, 2003. |
| R. M. Dabbas, J. W. Fowler, D. A. Rollier, D. McCarville, "Multiple
Response Optimization Using Mixture-Designed Experiments And Desirability
Functions In Semiconductor Scheduling," International Journal of
Production Research, Vol. 41, No. 5, 939-961, 2003. |
| J. Dai and S. Neuroth, "DPSS Scheduling Policies in Semiconductor
Wafer Fabs," Proceedings of the International Conference on Modeling
and Analysis of Semiconductor Manufacturing (MASM 2002), Editors G. T.
Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002.
194-199. |
| J. E. Dayhoff and R. W. Atherton, "Signature Analysis of Dispatch
Schemes in Wafer Fabrication," IEEE Transactions on Components,
Hybrids, and Manufacturing Technology, Vol. CHMT-9, No. 4, 518-525, 1987. |
| I. Duenyas, J. W. Fowler, and L. W. Schruben, "Planning and
Scheduling in Japanese Semiconductor Manufacturing," Journal of
Manufacturing Systems, Vol. 13, No. 5, 1994. |
| H. E. Fargher, M. A. Kilgore, P. J. Kline, and R. A. Smith, "Planner
And Scheduler For Semiconductor Manufacturing," IEEE Transactions on
Semiconductor Manufacturing, Vol. 7, No. 2, 117-126, 1994. |
| P. G. Glassey, "A Comparison of Release Rules Using BLOCS/M
Simulations," Master of Science in Engineering Project Report,
Engineering Systems Research Center, the University of California at
Berkeley, 1990. |
| H. Gurnani, and P. K. Johri, "A Study of Performance Objectives in
the Scheduling of Manufacturing Lines," Journal of Manufacturing
Systems, Vol. 10, No. 5, 422-429, 1991. |
| O. Holthaus and C. Rajendran, "Efficient Dispatching Rules for
Scheduling in a Job Shop," International Journal of Production
Economics, Vol. 48, No. 1, 87-105, 1997. |
| Bo-Wei Hsieh, Shi-Chung Chang, Chun-Hung Chen, and Ming-Chen Chang, "Efficient Composition of Good Enough Dispatching Policies for Semiconductor Manufacturing," 2003 IEEE International Symposium on Semiconductor Manufacturing (ISSM '03), 67-70, 2003. The authors are from Via Technol. Inc., Hsin-Tien, Taiwan. |
| L. Huiran, J. Zhibin, Lee Yen Fei, and Ko Chen Pin, "Real Time Scheduler for Wafer Foundry Fab with Object-Oriented Petri Nets," 2003 IEEE International Symposium on Semiconductor Manufacturing (ISSM '03), 319-322, 2003. The authors are from Dept. of Ind. Eng. & Manage., Shanghai Jiaotong Univ., China. |
| Y.-F. Hung, "Scheduling of Mask Shop E-Beam Writers," IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 1, 165-172, 1998. |
| Y. Ishii, "An Effective Method of Dispatching to Realize High
Productivity for Flash Memory Manufacturing," Proceedings of the 2004
International Symposium on Semiconductor Manufacturing (ISSM 2004), Tokyo,
Japan, 2004. |
| V. Jain, R. Swarnkar, and M. K. Tiwari, "Modelling and Analysis of
Wafer Fabrication Scheduling Via Generalized Stochastic Petri Net and
Simulated Annealing," International Journal of Production Research,
Vol. 41, No. 15, 3501-3527, 2003. |
| J. B. Jensen, M. K. Malhotra, and P. R. Philipoom, "Family-Based
Scheduling of Shops with Functional Layouts," International Journal of
Production Research, Vol. 36, No. 10, 2687-2700, 1998. |
| S. Jin and S. J. Mason, "Rescheduling Strategies for Complex Job
Shops," Proceedings of the International Conference on Modeling and
Analysis of Semiconductor Manufacturing (MASM 2002), Editors G. T. Mackulak,
J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002. 90-94. |
| P. K. Johri, "Practical Issues in Scheduling and Dispatching in
Semiconductor Wafer Fabrication," Journal of Manufacturing Systems,
Vol. 12, No. 6, 474-485, 1993. |
| P. K. Johri, "Dispatching in an Integrated Circuit Wafer Fabrication
Line," Proceedings of the 1989 Winter Simulation Conference,
Washington, DC, 918-921, 1989. |
| J. J. Kanet and Z. Zhou, "A Decision Theory Approach to Priority
Dispatching for Job Shop Scheduling," Production and Operations
Management, Vol. 2, No. 1, 2-14, 1993. |
| R. M. Kerr, "Expert Systems In Production Scheduling: Lessons From A
Failed Implementation," Journal of Systems and Software, Vol. 19, No.
2, 123-130, 1992. |
| J-H Kim, T-E Lee, and H-Y Lee, "Scheduling of Dual-Armed Cluster
Tools with Time Constraints," Proceedings of the International
Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM
2002), Editors G. T. Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ,
April 10-12, 2002. 36-41. |
| J. H. Kim, T. E. Lee, H. Y. Lee, D. B. Park, "Scheduling Analysis of
Time-Constrained Dual-Armed Cluster Tools," IEEE Transactions on
Semiconductor Manufacturing, Vol. 16, No. 3, 521-534, 2003. |
| P. R. Kumar, "Scheduling Semiconductor Manufacturing Plants,"
IEEE Control Systems Magazine, Vol. 14, No. 6, 33-40, 1994. |
| F. S. C. Lam, B. C. Lin, C. Sriskandarajah, and H. Yan, "Scheduling
to Minimize Product Design Time Using a Genetic Algorithm,"
International Journal of Production Research, Vol. 37, No. 6, 1369-1386,
1999. |
| M. R. Lambrecht, P. L. Ivens, and N. J. Vandaele, "ACLIPS: A Capacity
and Lead Time Integrated Procedure for Scheduling," Management Science,
Vol. 44, No. 11, 1548-1561, 1998. |
| R. C. Leachman, "Production Planning and Scheduling Practices Across
the Semiconductor Industry," Department of Industrial Engineering and
Operations Research, Univ. of California at Berkeley, 1-30, 1994. |
| C.-E. Lee and C.-W. Chen, "A Dispatching Scheme Involving Move
Control and Weighted Due Date for Wafer Foundries," IEEE Transactions
on Components, Packaging, and Manufacturing Technology. Part C:
Manufacturing, Vol. 20, No. 4, 268-277, 1997. |
| C-Y Lee, T. C. E. Cheng, and B. M. Lin, "Minimizing the Makespan in
the 3-Machine Assembly-Type Flowshop Scheduling Problem," Management
Science, Vol. 39, No. 5, 616-625, 1993. |
| C-Y Lee, L. A. Martin-Vega, R. Uzsoy, and J. Hinchman,
"Implementation of a Decision Support System for Scheduling
Semiconductor Test Operations," Research Report No. 92-6, Department of
Industrial and Systems Engineering, University of Florida, 1992. |
| C-Y Lee and R. Uzsoy, "A New Dynamic Programming Algorithm for the
Parallel Machine Total Weighted Completion Time Problem," Research
Memorandum No. 91-92, Purdue University Department of Industrial
Engineering, 1991. |
| H. S. Lee and F. Tsai, "A Preemptive Dynamic Job Shop Scheduling
System," Proceedings of the IBM International Manufacturing
Productivity Symposium, IBM East Fishkill, New York, October 12-15, 1993. |
| S. Li, T. Tang, and D. W. Collins, "Minimum Inventory Variability
Schedule with Applications in Semiconductor Fabrication," IEEE
Transactions on Semiconductor Manufacturing, Vol. 9, No. 1, 145-149, 1996. |
| Shing-Ko Liang and Chia-Nan Wang, "Modularized Simulation for Lot Delivery Time Forecast in Automatic Material Handling Systems of 300mm Semiconductor Manufacturing," International Journal of Advanced Manufacturing Technology, Vol. 26, No. 5, 645-652, 2005. |
| D-Y Liao, S-C Chang, S-R Yen, and C-C Chien, "Daily Scheduling for
R&D Semiconductor Fabrication," Proceedings of the IEEE
International Conference on Robotics and Automation, Vol. 3, 77-82, 1992. |
| J. T. Lin and S.-C. Huang, "An Interactive Scheduler for a Wafer
Probe Centre in Semiconductor Manufacturing," International Journal of
Production Research, Vol. 36, No. 7, 1883-1900, 1998. |
| Y-T Lin, "Decision Tree Dispatching Model for Semiconductor
Tools," Proceedings of the 2004 International Symposium on
Semiconductor Manufacturing (ISSM 2004), Tokyo, Japan, 2004. |
| Wang Lixin, Francis Tay Eng Hock, and Lee Loo Hay (National University of
Singapore), "Scheduling MEMS Manufacturing," Proceedings of the
2000 Winter Simulation Conference, 2000. |
| S. X. C. Lou and G. van Ryzin, "Optimal Control Rules for Scheduling
Job Shops," Annals of Operations Research, Vol. 17, 233-248, 1989. |
| S. J. Mason, S. Jin, and C. M. Wessels, "Rescheduling Strategies for
Minimizing Total Weighted Tardiness in Complex Job Shops,"
International Journal of Production Research, Vol. 42, No. 3, 613-628, 2004. |
| S. J. Mason and K. Oey, "Scheduling Complex Job Shops Using
Disjunctive Graphs: A Cycle Elimination Procedure," International
Journal of Production Research, Vol. 41, No. 5, 981-994, 2003. |
| T. C. McGuigan, "Modeling the Lot Selection Process in Semiconductor
Photolithography Processing," Proceedings of the 1992 Winter Simulation
Conference, (eds.) J. J. Swain, D. Goldsman, R. C. Crain, and J. R. Wilson,
885-889, 1992. |
| K. N. McKay, F. R. Safayeni, and J. A. Buzacott, "'Common Sense'
Realities Of Planning And Scheduling In Printed Circuit Board
Production," International Journal of Production Research, Vol. 33, No.
6, 1587-1603, 1995. |
| K. N. McKay, F. R. Safayeni, and J. A. Buzacott, "Job-Shop Scheduling
Theory: What is Relevant?" Interfaces, Vol. 18, No. 4, 84-90, 1988. |
| H. S. Min and Y. Yih, "Development of a Real-Time Multi-Objective
Scheduler for a Semiconductor Fabrication System," International
Journal of Production Research, Vol. 41, No. 10, 2345-2364, 2003. |
| L. Monch, "A Genetic Algorithm Heuristic Applied to Stepper
Scheduling," Proceedings of the International Conference on Modeling
and Analysis of Semiconductor Manufacturing (MASM 2002), Editors G. T.
Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002.
276-281. |
| T. Nakata, "Auxiliary Tool Scheduling for Robust Semiconductor
Manufacturing," Proceedings of the 2004 International Symposium on
Semiconductor Manufacturing (ISSM 2004), Tokyo, Japan, 2004. |
| J. Ou and L. M. Wein, "Dynamic Scheduling of A Production/Inventory
System with By-Products and Random Yield," Management Science, Vol. 41,
No. 6, 1000-1017, 1995. |
| I. M. Ovacik and R. Uzsoy, "Decomposition Methods for Scheduling
Semiconductor Testing Facilities," International Journal of Flexible
Manufacturing Systems, Vol. 8, No. 4, 357-388, 1996. |
| I. M. Ovacik and R. Uzsoy, "Exploiting Shop Floor Status Information
To Schedule Complex Job Shops," Journal of Manufacturing Systems, Vol.
13, No. 2, 73-84, 1994. |
| I. M. Ovacik and R. Uzsoy, "A Shifting Bottleneck Algorithm for
Scheduling Semiconductor Testing Operations," Journal of Electronics
Manufacturing, Vol. 2, 119-134, 1992. |
| W. L. Pearn, S. H. Chung, and M. H. Yang, “A Case Study on the Wafer
Probing Scheduling Problem,” Production Planning and Control, Vol. 13, No.
1, 66-75, 2002. |
| W. L. Pearn, S. H. Chung, and M. H. Yang, "Minimizing the Total
Machine Workload for the Wafer Probing Scheduling Problem," IIE
Transactions, Vol. 34, No. 2, 211-220, 2002. |
| W. L. Pearn, S. H. Chung, and M. H. Yang, "The Wafer Probing
Scheduling Problem (WPSP)," Journal of the Operational Research
Society, Vol. 53, No. 8, 864-874, 2002. |
| C. N. Perry and R. Uzsoy, "Reactive Scheduling Of A Semiconductor
Testing Facility," Proceedings of the 15th IEEE/CHMT International
Electronics Manufacturing Technology (IEMT) Symposium, Santa Clara, CA,
191-194, 1993. |
| E. Peyrol, P. Floquet, L. Pibouleau, and S. Domenech, "Scheduling And
Simulated Annealing Application To A Semiconductor Circuit Fabrication
Plant," Computers & Chemical Engineering, Vol. 17, 39-44, 1993. |
| M. Pinedo, Scheduling Theory, Algorithms and Systems, Prentice Hall,
Englewood Cliffs, NJ, 1995. |
| C. Rajendran and O. Holthaus, "A Comparative Study of Dispatching
Rules in Dynamic Flowshops and Jobshops," European Journal of
Operational Research, Vol. 116, No. 1, 156-170, 1999. |
| S. Rostami and B. Hamidzadeh," An Optimal Residency-Aware Scheduling
Technique for Cluster Tools with Buffer Module," IEEE Transactions on
Semiconductor Manufacturing, Vol. 17, No. 1, 68-73, 2004. |
| R. Roy, "Scheduling And Control, Performance Measures And Discrete
Event Simulation," Journal of the Operational Research Society, Vol.
49, No. 2, 151-156, 1998. |
| K. Saito and S. Arima, "A Novel Dispatch Algorithm Reducing Adjustment Rate in Processing a Product-Mix: Comparison of FCFS, SPT, and New Algorithm," 2003 IEEE International Symposium on Semiconductor Manufacturing (ISSM '03), 285-288, 2003. The authors are from Univ. of Aizu, Fukushima, Japan. |
| T. Sakurai, M. Yoshizawa, S. Tazawa, and T. Takeda, "An LSI Delivery
Management Technology using Lot-sampling Scheduling for an ASIC Production
Line," Proceedings of the IBM International Manufacturing Productivity
Symposium, IBM East Fishkill, New York, October 12-15, 1993. |
| R. Sandell, "Scheduling Policies in Semiconductor Manufacturing
Systems SEMATECH Technology Transfer # 95062884A-XFR, July 31, 1995. |
| Y. X. Shen and R. C. Leachman, "Stochastic Wafer Fabrication
Scheduling," IEEE Transactions on Semiconductor Manufacturing, Vol. 16,
No. 1, 2-14, 2003. |
| Jiun Shiu, Ting-Kai Hwang, Yen-Wen Huang, Chiou-Ming Tsai, Wei-Min Su, Ya
Cheng, Shi-Chung Chang, Cheng-Chung Chien, "FASE: A Scheduling
Environment For Semiconductor Fabrication," Proceedings of the
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology
Symposium, Austin, TX, 34-41, 1996. |
| S. Sidhu, "An Intelligent Scheduling System for Semiconductor Wafer
Fabrication," Intellection, Dallas, TX. |
| J. V. Simons, Jr. and W. P. Simpson III, "An Exposition of Multiple
Constraint Scheduling As Implemented In The Goal System (formerly
DISASTER)", Production and Operations Management, Vol. 6, No. 1, 3-24,
1997. |
| T. W. Sloan, "Shop-Floor Scheduling of Semiconductor Wafer Fabs:
Exploring the Influence of Technology, Market, and Performance
Objectives," IEEE Transactions on Semiconductor Manufacturing, Vol. 16,
No. 2, 281-289, 2003. |
| T. W. Sloan and J. G. Shanthikumar, "Using In-Line Equipment
Condition and Yield Information for Maintenance Scheduling and Dispatching
in Semiconductor Wafer Fabs," IIE Transactions, Vol. 34, No. 2,
191-209, 2002. |
| S. F. Smith, "Knowledge-Based Production Management," Production
Planning and Control, Vol. 3, 350-380, 1992. |
| T. Takeda, S. Tazawa, K. Wada, and E. Arai, "On-Line Scheduler For
ASIC Manufacturing Line Management," IEICE Transactions on Electronics,
Vol. E78-C, No. 3, 241-247, 1995. |
| V. Tardiff and M. L. Spearman, "Diagnostic Scheduling In
Finite-Capacity Production Environments," Computers & Industrial
Engineering, Vol. 32, No. 4, 867-878, 1997. |
| F. E. H. Tay, L. H. Lee, and L. X. Wang, "Production Scheduling of a
MEMS Manufacturing System with a Wafer Bonding Process," Journal of
Manufacturing Systems, Vol. 21, No. 4, 287-301, 2002. |
| R. Uzsoy, L. A. Martin-Vega, C-Y Lee, and P. A. Leonard, "Production
Scheduling Algorithms for a Semiconductor Test Facility," IEEE
Transactions on Semiconductor Manufacturing, Vol. 4, No. 4, 270-279, 1991. |
| R. Uzsoy, C-Y Lee, L. A. Martin-Vega, and J. Hinchman, "Scheduling
Semiconductor Test Operations: Optimization and Approximation,"
Research Memorandum No. 91-11, Purdue University Department of Industrial
Engineering, 1991. |
| R. Uzsoy, C-Y Lee, and L. A. Martin-Vega, "Scheduling Semiconductor
Test Operations: Minimizing Maximum Lateness and Number of Tardy Jobs on a
Single Machine", Research Memorandum No. 91-20, Purdue University
Department of Industrial Engineering, 1991. |
| G. L. Vairaktarakis and C-Y Lee, "The Single Machine Problem to
Minimize Total Tardiness Subject to Minimum Number of Tardy Jobs,"
Department of Industrial and Systems Engineering, University of Florida. |
| Zhongjie Wang and Qidi Wu, "Multiobject Optimal Scheduling for Semiconductor Manufacturing Line Based on Satisfactory Control," Proceedings of the 2002 American Control Conference, Vol. 2, 1603-1608, 2002. |
| K. P. White, Jr. and R. V. Rogers, "Job-Shop Scheduling: Limits of
the Binary Disjunctive Formulation," International Journal of
Production Research, Vol. 28, No. 12, 2187-2200, 1990. |
| R. J. Wittrock, "Scheduling Algorithms for Flexible Flow Lines,"
IBM J. Res. Develop., 401-412, 1985. |
| H. H. Xiong and M. C. Zhou, "Scheduling of Semiconductor Test
Facility via Petri Nets and Hybrid Heuristic Search, IEEE Transactions on
Semiconductor Manufacturing, Vol. 11, No. 3, 384-393, 1998. |
| J. Yang and T. S. Chang, "Multiobjective Scheduling For IC Sort And
Test With A Simulation Testbed," IEEE Transactions on Semiconductor
Manufacturing, Vol. 11, No. 2, 304-315, 1998. |
| H. J. Yoon, and D. Y. Lee, "Deadlock-Free Scheduling of
Photolithography Equipment in Semiconductor Fabrication," IEEE
Transactions on Semiconductor Manufacturing, Vol. 17, No. 1, 42-54, 2004. |
| H.J. Yoon and D.Y. Lee, "Online Scheduling of Integrated Single-Wafer Processing Tools with Temporal Constraints," IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 3, 390-398, 2005. |
| R.-C. You, C.-S. Wu, L.-R. Lin, H.-L. Chu, Y.-K. Chang, "Dispatching
System Hit Rate Improvement In 300mm Fab," Proceedings of the 2002
International Symposium on Semiconductor Manufacturing (ISSM2002), Tokyo,
Japan, 2002. |
| M. Zweben and M. Fox (eds), Intelligent Scheduling, Morgan and Kaufman,
San Mateo, 1994. Includes chapter by Karl Kempf: "Intelligently
Scheduling Semiconductor Wafer Fabrication." |
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