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A Bibliography on Capacity Modeling for Semiconductor Manufacturing
Section 32: Rework
 | S. J. Hood, "Detail vs. Simplifying Assumptions for Simulating
Semiconductor Manufacturing Lines," Proceedings of the Ninth IEEE
International Electronics Manufacturing Technology Symposium, 103-108, 1990. |
 | M. E. Kuhl, and G. R. Laubisch, "A Simulation Study of Dispatching Rules and Rework Strategies in Semiconductor Manufacturing," IEEE 2004 Advanced Semiconductor Manufacturing Conference (ASMC '04), 325-329, 2004. Authors are from Ind. & Syst. Eng. Dept., Rochester Inst. of Technol., NY, USA. |
 | D. Y. Sha, L. F. Hsieh, and K. J. Chen, "Wafer Rework Strategies at
the Photolithography Stage," International Journal of Industrial
Engineering - Theory, Applications, and Practice, Vol. 8, No. 2, 122-130,
2001. |
 | A.M. Zargar and B. Ehteshami, "Tradeoffs in Cycle Time Management:
Reworked Bonus Lots," Proceedings of the Summer Computer Simulation
Conference, 1039-1043, 1991. |

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