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A Bibliography on Capacity Modeling for Semiconductor Manufacturing
Section 17: Lead Times
 | E. Akcali, K. Nemoto, and R. Uzsoy, "Cycle-Time Improvements for
Photolithography Process in Semiconductor Manufacturing," IEEE
Transactions on Semiconductor Manufacturing, Vol. 14, No. 1, 48-56,
2001. |
| T. Beeg, "Wafer Fab Cycle Forecast under Changing Loading Situations," IEEE 2004 Advanced Semiconductor Manufacturing Conference (ASMC '04), 339-343, 2004. Author is from Infineon Technol. AG, Dresden, Germany. |
| J. L. Berry, N. Pierce, L. Serrano, S. Stankus, R. Darrington, W. Scott, B. Sinclair, "The Positive Cycle Time Impact of Closely Monitoring your Factory's Critical Tools," IEEE 2000 Advanced Semiconductor Manufacturing Conference (ASMC '00), 75-80, 2000. The authors are from Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX. |
| F. G. Boebel and O. Ruelle, "Cycle Time Reduction Program at ACL,"
Proceedings of the 1996 IEEE/SEMI Advanced Semiconductor Manufacturing
Conference, Cambridge, MA, 165-168, 1996. |
| J. Bonal, M. Fernadez, O. Maire-Richar, S. Aparicio, R. Oliva, S. Garcia,
B. Gonzalez, L. Rodriguez, M. Rosendo, J.C. Villacieros, and J.Becerro,
"A Statistical Approach To Cycle Time Management," Proceedings of
the 2001 Advanced Semiconductor Manufacturing Conference (ASMC 01), Munich,
Germany, 2001. |
| J. Bonal, L. Rios, C. Ortega, S. Aparicio, M. Fernandez, M. Rosendo, A.
Sanchez, and S. Malvar, "Productivity Improvement Through Cycle Time
Analysis," Working Paper, Lucent Technologies, Madrid, 1996. |
| J. Bonal, A. Sadai, C. Ortega, S. Aparicio, M. Fernandez, R. Oliva, L.
Rodriguez, M. Rosendo, A. Sanchez, E. Paule, and D. Ojeda, "Management
of Multiple-Pass Constraints," Proceedings of the 1998 Advanced
Semiconductor Manufacturing Conference (ASMC98), 1998. |
| S. Brown, J. Domaschke, and F. Leibl, "Cycle Time Reductions for Test
Area Bottleneck Equipment", Proceedings of the Second Annual SEMI Test,
Assembly, and Packaging Automation and Integration Conference, B1-B5,
1998. |
| P. Burggraaf, "Is Total Single Wafer the Fundamental Change the
Industry Needs? (Trecenti Technologies is Bringing Proprietary Advantage
back to Semiconductor Manufacturers), Solid State Technology, March 2003,
Vol. 46, No. 3, S20(3). |
| A. W. Chan, A. Satir, and V. J. Thomson, "Reduction of Cycle Time in
Manufacturing Using Simulation," Proceedings of the International
Conference on Computer Applications in Production and Engineering (CAPE
'97), Detroit, MI, 359-368, November 1997. |
| C. Y. J. Chen, E. I. George, and V. Tardif, "A Bayesian Model of
Cycle Time Prediction," IIE Transactions, Vol. 33, No. 10, 921-930,
2001. S. H. Chung and H. W. Huang, "Cycle Time Estimation for Wafer Fab
with Engineering Lots," IIE Transactions, Vol. 34, No. 2, 105-118,
2002. |
| Yu-Chih Chen, K. L. Young, and J. Y. Chou, "Key Factor for New Technology Transfer on the R&D Cycle-Time System," Proceedings of the 2004 Semiconductor Manufacturing Technology Conference, 182-185, 2004. The authors are from Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan. |
| Wladyslaw Danielak and Lynn Weckwerth, "Increasing Capacity Together
With Reducing Cycle Time. A Look at Productivity Improvement Process at GaAs
Wafer Fab," Compound Semiconductor Manufacturing Expo, July 9-11,
2001. |
| L. Demeester and C. S. Tang, "Reducing Cycle Time at an IBM Wafer
Fabrication Facility," Interfaces, Vol. 26, No. 2, 34-49, 1996. |
| J. Domaschke, S. Brown, and F. Leibl, "No-Cost Applications for
Assembly Cycle Time Reduction," Proceedings of the Semicon West 1998
Technical Symposium on Semiconductor Packaging Technology, July 15-17, 1998,
San Jose. |
| J. Domaschke, S. Brown, J. Robinson, and F. Leibl, "Effective
Implementation of Cycle Time Reduction Strategies for Semiconductor Back-End
Manufacturing," Proceedings of the 1998 Winter Simulation Conference,
Washington, DC, D. J. Medeiros, E. F. Watson, J. S. Carson, and M. S.
Manivannan, eds, 985-992. |
| K. Fordyce and G. Sullivan, "Cycle Time Versus Machine Utilization:
Moving Along the Curve vs. Shifting the Curve," IBM Technology Report
No. TR 21.1440, 1991. |
| J. W. Fowler, S. Park, G. T. Mackulak, and D. L. Shunk, "Efficient
Cycle Time-Throughput Curve Generation Using A Fixed Sample Size
Procedure," International Journal of Production Research, Vol. 39, No.
12, 2595-2613, 2001. |
| N. S. Grewal, A. C. Bruska, T. M. Wulf, and J. K. Robinson,
"Integrating Targeted Cycle-Time Reduction into the Capital Planning
Process," Proceedings of the 1998 Winter Simulation Conference,
Washington, DC, D. J. Medeiros, E. F. Watson, J. S. Carson, and M. S.
Manivannan, eds, 1005-1010. |
| A. Gupta and K. Potti, "Applications of Simulation Modeling at a
Texas Instruments DMOS5 Wafer Fab," Proceedings of the International
Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM
2002), Editors G. T. Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ,
April 10-12, 2002. 137-140. |
| S. Hood, P. Welch, F. Chance, C. Clemons, and D. Robideau, "Cycle
Time Behavior in Semiconductor Manufacturing," Proceedings of the 1991
Manufacturing Productivity Symposium, IBM, 1991. |
| W. J. Hopp, M. L. Spearman, and D. L. Woodruff, "Practical Strategies
for Lead Time Reduction," Manufacturing Review, Vol. 3, No. 2, 78-84,
1990. |
| G. W. Horn and W. A. Podgorski, "A Focus on Cycle-Time Vs. Tool
Utilization "Paradox" with Material Handling Methodology,"
Proceedings of the 1998 Advanced Semiconductor Manufacturing Conference and
Workshop (ASMC 98), Boston, MA, 405-412, 1998. |
| H-M Hsu, J-R Chen, H-H Woo, and M-C Wu, "A Cycle Time Based Capacity
Planning System," Proceedings of the International Conference on
Modeling and Analysis of Semiconductor Manufacturing (MASM 2002), Editors G.
T. Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002.
148-152. |
| M. Janakiram, "Cycle Time Reduction at Motorola's ACT Fab,"
Proceedings of the 1996 Advanced Semiconductor Manufacturing Conference and
Workshop (ASMC 96), Boston, MA, 465-469, 1996. |
| I. Kim and C. S. Tang, "Lead Time And Response Time In A Pull
Production Control System," European Journal of Operational Research,
Vol. 101, No. 3, 474-485, 1997. |
| S. Johnishi, K. Ozawa and N. Satoh, "Dynamic X-Factor Application for
Optimizing Lot Control for Agile Manufacturing," Proceedings of the
2002 International Symposium on Semiconductor Manufacturing (ISSM2002),
Tokyo, Japan, 2002. |
| R. T. Johnson, F. Yang, B. E. Ankenman, and B. L. Nelson, "Nonlinear
Regression Fits for Simulated Cycle Time Vs. Throughput Curves for
Semiconductor Manufacturing," Proceedings of the 2004 Winter Simulation
Conference, Washington, DC, Dec. 5-8, 2004. |
| T. Kawase, "Cycle Time Reduction by BSA (Bottleneck Starvation
Avoidance)," Proceedings of the 2002 International Symposium on
Semiconductor Manufacturing (ISSM2002), Tokyo, Japan, 2002. |
| D. E. Kirjassoff, "Large-Scale Business Process Improvement: Reducing
Total Make-To- Market Cycle Time," Proceedings of the 1993 IEEE/SEMI
International Semiconductor Manufacturing Science Symposium, 86-88,
1993. |
| M. Kishimoto, K. Ozawa, K. Watanabe, and D. Martin, "Optimized
Operations by Extended X-Factor Theory Including Unit Hours Concept,"
IEEE Transactions on Semiconductor Manufacturing, Vol. 14, No. 3, 187-195,
2001. |
| H. Koike, F. Matsuoka, S. Hohkibara, E. Fukuda, K. Tomioka, H. Miyajima,
K. Muraoka, N. Hayasaka, and M. Kimura, "Quick-Turnaround-Time
Improvement For Product Development And Transfer To Mass Production,"
IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 1, 54-62,
1998. |
| R. C. Leachman, J. Kang, V. Lin, “SLIM: Short Cycle Time and Low
Inventory in Manufacturing at Samsung Electronics,” Interfaces, Vol. 32,
No 1, 2002. |
| Y. H. Lee and T. Kim, "Manufacturing Cycle Time Reduction Using
Balance Control in the Semiconductor Fabrication Line," Production
Planning & Control, Vol. 13, No. 6, 529-540, 2002. |
| G. Leonovich, "An Approach for Optimizing WIP/Cycle Time/Output in a
Semiconductor Fabricator," 1994 IEEE/CPMT International Electronics
Manufacturing Technology Symposium. |
| Y. H. Lin and C. E. Lee, "A WIP Estimation Model For Wafer
Fabrication," International Journal of Industrial Engineering - Theory,
Applications and Practice, Vol. 9, No. 3, 222-237, 2002. |
| C. Ling-Ho and S. Muralitharan, "Method to Enable Visibility and
Forecast in Fab Cycletime Performance," Proceedings of the 2002
International Symposium on Semiconductor Manufacturing (ISSM2002), Tokyo,
Japan, 2002. |
| D. P. Martin, "The Advantages of Using Short Cycle Time Manufacturing
(SCM) Instead of Continuous Flow Manufacturing (CFM)," Future Fab
International, Volume 9, 1999. (abstract currently available from www.fabtech.org). |
| D. P. Martin, "Key Factors in Designing a Manufacturing Line to
Maximize Tool Utilization and Minimize Turnaround Time," IBM Technology
Products, Essex Junction, VT, 1994. |
| D. P. Martin, "Maximizing Productivity Improvements Using Short Cycle Time Manufacturing (SCM) Concepts in a Semiconductor Manufacturing Line," IEEE 2000 Advanced Semiconductor Manufacturing Conference (ASMC '00), 63-67, 2000. The authors are from IBM Microelectron. Div., Essex Junction, VT. |
| J. E. McNeill, G. T. Mackulak, and J. W. Fowler (Arizona State
University), "Indirect Estimation of Cycle Time Quantiles from Discrete
Event Simulation Models Using the Cornish-Fisher Expansion,"
Proceedings of the 2003 Winter Simulation Conference, S. Chick, P. J.
Sánchez, D. Ferrin, and D. J. Morrice, eds., 2003. |
| D. Mercier and O. Bonnin, "300mm Semiconductor Manufacturing Cycle
Time Strategy Assessment Through a DOE Based on Dynamic Simulation,"
Proceedings of the International Conference on Modeling and Analysis of
Semiconductor Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W.
Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002. 122-125. |
| K. Nemoto, E. Akcali, and R. Uzsoy, “Quantifying the Benefits of Cycle
Time Reduction in Semiconductor Wafer Fabrication,” IEEE Transactions on
Electronics Packaging Manufacturing, Vol. 23, No. 1, 39-47, 2000. |
| B. Ng, B. G. Ferrin, and J. N. Pearson, "The Role Of
Purchasing/Transportation In Cycle Time Reduction," International
Journal of Operations & Production Management, Vol. 17, No. 5-6,
574-591,536, 1997. |
| S. Park, J. W. Fowler, G. T. Mackulak, J. B. Keats, and W. M. Carlyle,
"D-Optimal Sequential Experiments for Generating A Simulation-Based
Cycle Time-Throughput Curve," Operations Research, Vol. 50, No. 6,
981-990, 2002. |
| K. Potti and M. Whitaker, "CT Reduction at a Major Texas Instruments
Wafer Fab," Proceedings of the 14th Annual IEEE/SEMI Advanced
Semiconductor Manufacturing Conference and Workshop, Munich, Germany, 2003. |
| A. Raddon and B. Grigsby, “Throughput Time Forecasting Model,”
Proceedings of the 1997 IEEE/SEMI Advanced Semiconductor Manufacturing
Conference, 430-433, 1997. |
| T. Sada, R. A. Yuen, M. Ichikawa, M. Yamada, and K. Kabata, "Simple Tool of Analysis for Cycle Time Reduction," 2001 IEEE International Symposium on Semiconductor Manufacturing (ISSM '01), 79-82, 2001. The authors are from NEC Electron., Roseville, CA. |
| F. Sadjadi and T. Baker, "Comprehensive Cycle Time Reduction Program at AMD's Fab25," 2001 IEEE International Symposium on Semiconductor Manufacturing (ISSM '01), 95-98, 2001. The authors are from Adv. Micro Devices Inc., Austin, TX. |
| L. Sattler, "Using Queueing Curve Approximations in a Fab to
Determine Productivity Improvements," Proceedings of the 1996 Advanced
Semiconductor Manufacturing Conference and Workshop (ASMC 96), Boston, MA,
140-145, 1996. |
| T. Y. Tseng, T. F. Ho, and R. K. Li, "Mixing Macro and Micro Flowtime
Estimation Model: Wafer Fab Example," International Journal of
Production Research, Vol. 37, No. 11, 2447-2461, 1999. |
| E. van der Laan, M. Salomon, and R. Dekker, "An Investigation of
Lead-Time Effects in Manufacturing/Remanufacturing Systems Under Simple PUSH
and PULL Control Strategies, European Journal of Operational Research, Vol.
115, No. 1, 195-214, 1999. |
| J. G. Wacker, "A Theoretical Model Of Manufacturing Lead Times And
Their Relationship To A Manufacturing Goal Hierarchy," Decision
Sciences, 483-517, Vol. 27, No. 3, 1996. |
| O. Wight, "Input/Output Control: A Real Handle on Lead Time,"
Production and Inventory Management, 3rd Qtr., 1970. |
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