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A Bibliography on Capacity Modeling for Semiconductor Manufacturing
Section 4: Batching
 | E. Akçali and R. Uzsoy (Purdue University) and D. G. Hiscock, A. L.
Moser, and T. J. Teyner (Intersil), "Alternative Loading and
Dispatching Policies for Furnace Operations in Semiconductor Manufacturing:
A Comparison by Simulation," Proceedings of the 2000 Winter Simulation
Conference, 2000. |
| A. Avramidis, K. J. Healy, and R. Uzsoy, "Control of a
Batch-Processing Machine: A Computational Approach," International
Journal of Production Research, Vol. 36, No. 11, 3167-3181, 1998. |
| H. Balasubramanian, L. Monch, J. Fowler, and M. Pfund, "Genetic
Algorithm Based Scheduling of Parallel Batch Machines with Incompatible Job
Families to Minimize Total Weighted Tardiness," International Journal
of Production Research, Vol. 42, No. 8, 1621-1638, 2004. |
| J. W. Butterbaugh, "Strategies for Cycle Time Reduction in Batch Cleaning," IEEE 2004 Advanced Semiconductor Manufacturing Conference (ASMC '04), 52-56, 2004. Author is from FSI Int. Inc., Chaska, MN, USA. |
| V. Chandru, C-Y Lee, and R. Uzsoy, "Minimizing Total Completion Time
on A Batch Processing Machine with Job Families," Operations Research
Letters, Vol. 13, No. 2, 61-65, 1993. |
| V. Chandru, C-Y Lee, and R. Uzsoy, "Minimizing Total Completion Time
on Batch Processing Machines," International Journal of Production
Research, Vol. 31, No. 9, 2097-2121, 1993. |
| Pei-Chann Chang and Hui-Mei Wang, "A Heuristic for a Batch Processing Machine Scheduled to Minimise Total Completion Time with Non-Identical Job Sizes," International Journal Of Advanced Manufacturing Technology, Vol. 24, No. 7, 615-620, 2004. |
| Noah Chiou, Ivan Wang, Jerry Chang, and Topas Chang, "The Tool Efficiency Monitoring System Creation of Furnace Area in Semiconductor Manufacturing," Proceedings of the 2002 Semiconductor Manufacturing Technology Conference, 132-135, 2002. |
| G. L. Curry and B. L. Deuermeyer, "Renewal Approximations for the
Departure Processes of Batch Systems," IIE Transactions, Vol. 34, No.
2, 94-104, 2002. |
| G. Dobson and R. S. Nambimadom, "The Batch Loading and Scheduling
Problem," Working Paper No. QM 92-03, William E. Simon Graduate School
of Business Administration, University of Rochester, Rochester, NY,
1992. |
| G. Dobson and R. S. Nambimadom, "The Batch Loading and Scheduling
Problem," Operations Research, Vol. 49, No. 1, 52-65, 2001. |
| I. Duenyas and J. J. Neale, "Stochastic Scheduling Of A Batch
Processing Machine With Incompatible Job Families," Annals of
Operations Research, Vol. 70, 191-220, 1997. |
| J. W. Fowler, N. Phojanamongkolkij, J. K. Cochran, D. C. Montgomery,
"Optimal Batching in a Wafer Fabrication Facility Using a Multiproduct
G/G/c Model with Batch Processing," International Journal of Production
Research, Vol. 40, No. 2, 275-292, 2002. |
| H. Gurnani, R. Anupindi, and R. Akella, "Control of Batch Processing
Systems in Semiconductor Wafer Fabrication Facilities," IEEE
Transactions on Semiconductor Manufacturing, Vol. 5, No. 4, 319-328, 1992.
Also available in the Proceedings of the 1991 IEEE International Conference
on Robotics and Automation, Sacramento, CA. |
| M. G Huang, P. L. Chang, and Y. C. Chou, "Analytic Approximations for
Multiserver Batch-Service Work-Stations with Multiple Process Recipes in
Semiconductor Wafer Fabrication," IEEE Transactions on Semiconductor
Manufacturing, Vol. 14, No. 4, 395-405, 2001. |
| D. S. Hochbaum and D. Landy, "Scheduling Semiconductor Burn-In
Operations to Minimize Total Flowtime," Operations Research, Vol. 45,
No. 6, 874-885, 1997. |
| K. Ibrahim, M. A. Chik, W. S. Nizam, N. L. Fern, and N. F. Za'bah, "Efficient Lot Batching System for Furnace Operation," IEEE 2003 Advanced Semiconductor Manufacturing Conference (ASMC '03), 175-187, 2003. The authors are from Silterra (M) Sdn Bhd, Kedah, Malaysia. |
| Y. Ikura and M. Gimple, "Efficient Scheduling Algorithms for a Single
Batch Processing Machine," Operations Research Letters, Vol. 5, No. 2,
61-65, 1986. |
| K. G. Kempf, R. Uzsoy, C. S. Wang, "Scheduling A Single Batch
Processing Machine With Secondary Resource Constraints," Journal of
Manufacturing Systems, Vol. 17, No. 1, 37-51, 1998. |
| C-Y Lee, R. Uzsoy and L. A. Martin-Vega, "Efficient Algorithms for
Scheduling Semiconductor Burn-In Operations," Operations Research, Vol.
40, No. 4, 764-775, 1992. |
| C.-L. Li and C.-Y. Lee, "Scheduling with Agreeable Release Times and
Due Dates on a Batch Processing Machine," European Journal of
Production Research, Vol. 96, No. 3, 564-569, 1997. |
| P. Meissner, A. Hegedus, J. Madok, R. Thakur, and G. Miner, "Thermal
Technologies for sub-100nm CMOS Scaling: Development Strategies,"
Proceedings of the 2001 ECS International Semiconductor Technology
Conference (ISTC), Shanghai, China, 2001. |
| L. Mönch and I. Habenicht (Technical University of Ilmenau),
"Simulation-Based Assessment of Batching Heuristics in Semiconductor
Manufacturing," Proceedings of the 2003 Winter Simulation Conference,
S. Chick, P. J. Sánchez, D. Ferrin, and D. J. Morrice, eds., 2003. |
| R. Noben, R. van Driel, T. Claasen-Vujcic, "Cycle Time Advantages of Mini Batch Manufacturing and Integrated Metrology in a 300 mm Vertical Furnace," 2001 IEEE International Symposium on Semiconductor Manufacturing (ISSM '01), 411-414, 2001. The authors are from ASM Int. NV, Bilthoven. |
| N. Phojanamongkolkij, J. W. Fowler, and J. K. Cochran, "Determining
Operating Criterion of Batch Processing Operations for Wafer
Fabrication," Journal of Manufacturing Systems, Vol. 21, No. 5,
363-379, 2002. |
| H.J.A. Rulkens, E.J.J. Van Campen, J. Van Herk, J. E. Rooda, "Batch
Size Optimization of a Furnace and Pre-Clean Area by Using Dynamic
Simulations," 1998 IEEE SEMI Advanced Semiconductor Manufacturing
Conference and Workshop, 439-444, 1998. |
| R. J. de Haut de Sigy, "Loading Control Policy for a Batch
Machine," Report No. LMP 90-001, Laboratory for Manufacturing and
Productivity, Massachusetts Institute of Technology, 1990. |
| G. Skinner and S. J. Mason, "A Genetic Algorithm for Scheduling
Parallel Batch-Processing Machines," Proceedings of the International
Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM
2002), Editors G. T. Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ,
April 10-12, 2002. 270-275. |
| L. Solomon, "The Effects of Setup on Batch Modeling in a
Semiconductor Manufacturing Facility," SEMATECH Technology Transfer #
95062885A-XFR, July 27, 1995. |
| L. Solomon, J. W. Fowler, M. Pfund, and P. H. Jensen, "The Inclusion
of Future Arrivals and Downstream Setups into Water Fabrication Batch
Processing Decisions," Journal of Electronics Manufacturing, Vol. 11,
No. 2, 149-159, 2002. |
| C. S. Sung and Y. I. Choung, "A Neural Network Approach for Batching
Decisions in Wafer Fabrication," International Journal of Production
Research, Vol. 37, No. 13, 3101-3114, 1999. |
| C. S. Sung and Y. I. Choung, "Minimizing Makespan on a Single Burn-In
Oven in Semiconductor Manufacturing," European Journal of Operations
Research, Vol. 120, No. 3, 559-574, 2000 |
| C. S. Sung, Y. I. Choung, and J. W. Fowler, "Heuristic Algorithm for
Minimizing Earliness-Tardiness on a Single Burn-In Oven in Semiconductor
Manufacturing," Proceedings of the International Conference on Modeling
and Analysis of Semiconductor Manufacturing (MASM 2002), Editors G. T.
Mackulak, J. W. Fowler, and A. Schoemig, Tempe, AZ, April 10-12, 2002.
217-222. |
| P. Tran-Gia and A. Schoemig, "Discrete-time Analysis of Batch Servers
with Bounded Idle Time," European Simulation Multiconference 1996, June
2-6, 1996, Budapest, Hungary. |
| R. Uzsoy and Y. Yang, "Minimizing Total Weighted Completion Time on a
Single Batch Processing Machine," Production and Operations Management,
Vol. 6, No. 1, 57-73, 1997. |
| De-Lung Wu, Hsi-Lo Lo, Cheng-Chung Pan, Yu-Ting Chang, and Chin-Lang Peng, "Automatically Form Batch via Real Time Dispatcher for Furnace Operation in 300 mm Fab," Proceedings of the 2004 Semiconductor Manufacturing Technology Conference, 29-32, 2004. The authors are from Powerchip Semicond. Corp., Hsinchu, Taiwan. |
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