|
Back
Up
Next
| |
A Bibliography on Capacity Modeling for Semiconductor Manufacturing
Section 3: Assembly, Test, and Packaging
 | A. Balakrishnan and F. Vanderbeck, "A Tactical Planning Model for
Mixed-Model Electronics Assembly Operations, Operations Research, Vol. 47,
No. 3, 395-409. |
| C-S Bong and K. V. Karuppiah, "Cycle-Time Reduction Under Product
Diversity in Semiconductor Back-End Manufacturing," Proceedings of the
International Conference on Modeling and Analysis of Semiconductor
Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W. Fowler, and A.
Schoemig, Tempe, AZ, April 10-12, 2002. 260-263. |
| P. Chandra and S. Gupta, "An Analysis of a Last-Station-Bottleneck
Semiconductor Packaging Line," Report No. 92-10-13, Research Working
Paper Series, Faculty of Management, McGill University, Montreal, Canada,
1992. |
| P. Chandra and S. Gupta, "Managing Batch Processors to Reduce Lead
Time in a Semiconductor Packaging Line," International Journal of
Production Research, Vol. 35, No. 3, 611-633, 1997. |
| P. B. Chevalier and L. M. Wein, "Inspection For Circuit Board
Assembly," Management Science, Vol. 43, No. 9, 1198-1213, 1997. |
| I. Duenyas and W. J. Hopp, "CONWIP Assembly with Deterministic
Processing and Random Outages," IIE Transactions, Vol. 24, No. 4,
97-110, 1992. |
| K. P. Ellis, Y. Lu, and E. K. Bish, "Scheduling of Wafer Test
Processes in Semiconductor Manufacturing," International Journal of
Production Research, Vol. 42, No. 2, 215-242, 2004 |
| J. Fowler, K. Knutson, and M. Carlyle, "Comparison and Evaluation of
Lot-To-Order Matching Policies for a Semiconductor Assembly and Test
Facility," International Journal of Production Research, Vol. 38, No.
8, 1841-1853, 2000. |
| T. Freed, R. C. Leachman, and K. H. Doerr, "A Taxonomy of Scheduling
Problems in Semiconductor Device Test Operations," Proceedings of the
International Conference on Modeling and Analysis of Semiconductor
Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W. Fowler, and A.
Schoemig, Tempe, AZ, April 10-12, 2002. 252-259. |
| W. G. Gilland, "A Simulation Study Comparing Performance of CONWIP
and Bottleneck- Based Release Rules," Production Planning and Control,
Vol. 13, No. 2, 211-219, 2002. |
| A. K. Gupta, and A. I. Sivakumar, "Approaches to Multiobjective
Scheduling Optimization in Semiconductor Back-End," Proceedings of the
International Conference on Modeling and Analysis of Semiconductor
Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W. Fowler, and A.
Schoemig, Tempe, AZ, April 10-12, 2002. 223-228. |
| M. Grunow, H. O. Gunther, and A. Fohrenbach, "Simulation-Based
Performance Analysis And Optimization Of Electronics Assembly
Equipment," International Journal of Production Research, Vol. 38, No.
17, 4247-4259, 2000. |
| K. R. Haberle, R. J. Burke, and R. J. Graves, "Cycle Time Estimation
Models for Printed Circuit Board Design," International Journal of
Production Research, Vol. 40, No. 4, 1017-1028, 2002. |
| K. Hadavi, W-L Hsu, M. Pinedo, and P. Spool, "Estimation of
Completion Times when Processing Plans Require Mergings of Batches." |
| J. W. Hermann, C.-Y. Lee and J. Hinchman, "Global Job Shop Scheduling
with A Genetic Algorithm," Production and Operations Management, Vol.
4, No. 1, 30-45, 1995. |
| M. S. Hillier and M. L. Brandeau, "Cost Minimization And Workload
Balancing In Printed Circuit Board Assembly," IIE Transactions, Vol.
33, No. 7, 547-557, 2001. |
| S. J. Jain, N. F. Choong, A. M. Aye, M. Luo, "Virtual Factory: an
Integrated Approach to Manufacturing Systems Modeling," International
Journal of Operations & Production Management, Vol. 21, No. 5-6,
594-608, 2001. |
| S. Jain, M. E. Johnson, and F. Safai, "Implementing Setup
Optimization on the Shop Floor," Operations Research, Vol. 43, No. 6,
843-851, 1996. |
| K. Jeevan, A. Parthiban, K. N. Seetharamu, I. A. Azid, G. A. Quadir,
"Optimization of PCB Component Placement using Genetic
Algorithms," Journal of Electronics Manufacturing, Vol. 11, No. 1,
67-79, 2002. |
| K. Knutson, K. Kempf, J. Fowler, and M. Carlyle, "Lot-to-Order
Matching for A Semiconductor Assembly And Test Facility," IIE
Transactions, Vol. 31, No. 11, 1103-1111, 1999. |
| J. E. Kobza, K. P. Ellis, and F. J. Vittes, "Improving Throughput for
an Electronic Assembly Line using a Constraint Analysis Methodology,"
Production Planning & Control, Vol. 13, No. 3, 262-273, 2002. |
| H. Kuhn and D. Quadt, "Lot Sizing and Scheduling in Semiconductor
Assembly - A Hierarchical Planning Approach," Proceedings of the
International Conference on Modeling and Analysis of Semiconductor
Manufacturing (MASM 2002), Editors G. T. Mackulak, J. W. Fowler, and A.
Schoemig, Tempe, AZ, April 10-12, 2002. 211-216. |
| K. R. Kumar and T. T. Narendran, "A Heuristic For Sequencing PCBs
With Due-Dates," International Journal of Operations & Production
Management, Vol. 17, No. 5-6, 446-467, 1997. |
| J. D. Liljegren, "Modeling Final Assembly and Test Processes in the
Semiconductor Industry," Proceedings of the 1992 Winter Simulation
Conference, (eds.) J. J. Swain, D. Goldsman, R. C. Crain, and J. R. Wilson,
856-860, 1992. |
| T.-H. Liu, A. J. C. Trappey, and F.-W. Chan, "A Scheduling System for
IC Packaging Industry Using STEP Enabling Technology," IEEE
Transactions on Components, Packaging, and Manufacturing Technology. Part C:
Manufacturing, Vol. 20, No. 4, 256-267, 1997. |
| H. Luss, M. B. Rosenwein, and E. T. Wahls, "Integration of Planning
and Execution: Final-Assembly Sequencing," AT&T Technical Journal,
99-109, July/August 1990. |
| R. W. T. Mak, S. M. Gupta, K. Lam, "Modeling of Material Handling
Hoist Operations in a PCB Manufacturing Facility," Journal of
Electronics Manufacturing, Vol. 11, No. 1, 33-50, 2002. |
| S. T. McCormick, M. L. Pinedo, S. Shenker, and B. Wolf, "Sequencing
in an Assembly Line with Blocking to Minimize Cycle Time," Operations
Research, Vol. 37, No. 6, 925-935, 1989. |
| M. Pfund, L. Yu, J. W. Fowler, and M. Carlyle, "The Impacts of
Variability on Scheduling Approaches for a Printed Wiring Board Assembly
Operation," Journal of Electronics Manufacturing, Vol. 11, No. 1,
19-31, 2002. |
| T. Sawik, A. Schaller, and T. M. Tirpak, "Scheduling of Printed
Wiring Board Assembly in Surface Mount Technology Lines," Journal of
Electronics Manufacturing, Vol. 11, No. 1, 1-17, 2002. |
| S. Seshadri and J. G. Shanthikumar, "Allocation of Chips to Wafers in
a Production Problem of Semiconductor Kits," Operations Research, Vol.
45, No. 2, 315-321, 1997. |
| D. D. Sheu and T. C. Wang, "Manufacturing Process Analysis for
Notebook Computer Plants: Circuit Board Assembly," International
Journal of Industrial Engineering-Theory Applications And Practice, Vol. 8
No. 4, 370-378, 2001. |
| D. D. Sheu, J. Lin, and P. Liao, "Benchmarking Manufacturing
Management Of Taiwan's IC Packaging Plants," International Journal of
Industrial Engineering, Vol. 7, No. 4, 365-370, 2001. |
| A. I. Sivakumar, "Simulation Based Cause and Effect Analysis of Cycle
Time Distribution in Semiconductor Backend," Proceedings of the 2000
Winter Simulation Conference, 2000. |
| I. Sivakumar, N. F. Choong and C. S. Chong, "Modeling Causes and
Effects of Semiconductor Backend Cycle Time," Solid State Technology,
Vol. 44, No. 12,51-53, 2001. |
| F. F. Suarez, M. A. Cusumano, and C. H. Fine, "An Empirical Study of
Manufacturing Flexibility in Printed Circuit Board Assembly,"
Operations Research, Vol. 44, No. 1, 223-240, 1996. |
| C. S. Sung, Y. I. Choung, J. M. Hong, and Y. H. Kim, "Minimizing
Makespan on a Single Burn-In Oven with Job Families and Dynamic Job
Arrivals," Computers & Operations Research, Vol. 29, No. 8,
995-1007, 2002. |
| Y. Tang and R. G. Qiu, "Integrated Design Approach for Virtual Production Line-Based Reconfigurable Manufacturing Systems," International Journal of Production Research, Vol. 42, No. 18, 3803-3822, 2004. |
| Y. Tang, M. C. Zhou, R. G. Qiu, "Virtual Production Lines Design For
Back-End Semiconductor Manufacturing Systems," IEEE Transactions on
Semiconductor Manufacturing, Vol. 16, No. 3, 543-550, 2003. |
| F. Tovia, S. J. Mason, and B. Ramasami, A Scheduling Heuristic for Maximizing Wirebonder Throughput, "IEEE Transactions on Electronics Packaging Manufacturing," Vol. 27, No. 2, 145-150, 2004. Also published in IEEE Transactions on Components, Packaging and Manufacturing Technology, Part C. The authors are from Dept. of Ind. Eng., Univ. of Arkansas, Fayetteville, AR, USA. |
| K. Wang and T. C. Hou, "Modelling and Resolving the Joint Problem of
Capacity Expansion and Allocation with Multiple Resources and a Limited
Budget in the Semiconductor Testing Industry," International Journal of
Production Research, Vol. 41, No. 14, 3217-3235. |
| M. Webster, C. Alder, and A. P. Muhlemann, "Subcontracting Within The
Supply Chain For Electronics Assembly Manufacture," International
Journal of Operations & Production Management, Vol. 17, No. 9-10,
827-841, 1997. |
| T. Yang and L. Tseng, "Solving A Multi-Objective Simulation Model
Using A Hybrid Response Surface Method And Lexicographical Goal Programming
Approach - A Case Study On Integrated Circuit Ink-Marking Machines,"
Journal of the Operational Research Society, Vol. 53, No. 2, 211-221, 2002. |
| Xiao-Feng Yin, Tay-Jin Chua, Feng-Yu Wang, Ming-Wei Liu, Tian-Xiang Cai, Wen-Jing Yan, Chin-Soon Chong, Ju-Ping Zhu, Mei-Yoke Lam, "A Rule-Based Heuristic Finite Capacity Scheduling System for Semiconductor Backend Assembly," International Journal of Computer Integrated Manufacturing, Vol. 17, No. 8, 733-749, 2004. |
|
