A Design of Experiments Methodology for Semiconductor Wafer Fab Capacity Planning
Authors:
Frank Chance
Chance Industrial Solutions
6900G Lake Drive
Dublin, California 94568
Jennifer Robinson
John Fowler
Arizona State University
Dept. of Industrial and Mgt. Systems Engr.
Box 875906
Tempe, Arizona 85287-5906
Ottmar Gihr
IBM Deutschland GmbH
Zentrum fur Produktionstechnik
Max-Eyth-Strafe 6, Postfach 266
7032 Sindelfingen, Germany
Ben Rodriguez
Nimble nv
Maaltecenter Blok G
Derbystraat 313
B-9051 Gent, Belgium
Lee Schruben
Cornell University
Department of Operations Research and Industrial Engr.
Ithaca, NY 14850
Abstract:
This paper describes a systematic method for analyzing the simultaneous impact of
various loss factors on the capacity of a semiconductor wafer fabrication facility.
Particular emphasis is placed on including cycle time in the capacity analysis. To that
end, a performance measure called cycle time constrained capacity is developed. The method
is illustrated through an investigation of 11 loss factors across four realistic factory
datasets. Suggestions are included on how to implement the methodology, so that the
methodology itself may be immediately transferrable, although specific results are factory
dependent.
Availability:
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