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Effective Implementation Of Cycle Time Reduction Strategies For Semiconductor Back-End
Manufacturing
Authors:
Joerg Domaschke
Siemens AG, HL MS
Balanstrasse 73
Munich 81541, GERMANY
Steven Brown
Siemens AG, HL MS
Balanstrasse 73
Munich 81541, GERMANY
Jennifer Robinson
Franz Leibl
Siemens Microelectronics Center
Koenigsbruecker Strasse 180
Dresden 01099, GERMANY
Abstract:
Using discrete-event simulation models, a study was conducted to evaluate the current
production practices of a high-volume semiconductor back-end operation. The overall goal
was to find potential areas for productivity improvement that would collectively yield a
60% reduction in manufacturing cycle time. This paper presents the simulation methodology
and findings pertaining to analysis of the Assembly, Burn-In, and Test operations. Many of
the recommendations identified can be implemented at no additional cost to the factory.
The most significant opportunities for improvement are in the Test area, the system
constraint. Additionally, the model is extremely sensitive to changes in operator staffing
levels, an accurate reflection of many back-end operations. The model shows that the
cumulative impact of these recommendations is a 41% reduction in average cycle time, a
significant contribution to the overall goal.
Keywords:
Manufacturing simulation; Semiconductor manufacturing; Cycle time reduction
Availability:
A PDF version of this document is available from the third author. This document was
published in the Proceedings of the 1998 Winter Simulation Conference, Washington,
DC, D. J. Medeiros, E. F. Watson, J. S. Carson, and M. S. Manivannan, eds, 985-992.
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